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| author | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:50 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:50 +0100 |
| commit | 0cdf9599b83fd20e297903b0204aec4f390ee98d (patch) | |
| tree | 6b83b0687beb681d2821e340bd26d8bda807cc91 /src/VeriFuzz/Verilog.hs | |
| parent | 8125f2c36d6306e20ce78f4056ef1b2fb6de61a2 (diff) | |
| download | verismith-0cdf9599b83fd20e297903b0204aec4f390ee98d.tar.gz verismith-0cdf9599b83fd20e297903b0204aec4f390ee98d.zip | |
Add Bit vector instead of using numbers
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 4d3b82c..dda3da1 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -18,14 +18,11 @@ module VeriFuzz.Verilog , randomMod , GenVerilog(..) , genSource - , getVerilog -- * Primitives -- ** Identifier , Identifier(..) - , getIdentifier -- ** Control , Delay(..) - , getDelay , Event(..) -- ** Operators , BinaryOperator(..) @@ -40,8 +37,7 @@ module VeriFuzz.Verilog , regExprId , regExpr , regSizeId - , regSizeMSB - , regSizeLSB + , regSizeRange , regConc -- ** Ports , PortDir(..) @@ -53,24 +49,8 @@ module VeriFuzz.Verilog , portName -- * Expression , Expr(..) - , exprSize - , exprVal - , exprId - , exprConcat - , exprUnOp - , exprPrim - , exprLhs - , exprBinOp - , exprRhs - , exprCond - , exprTrue - , exprFalse - , exprFunc - , exprBody - , exprStr , ConstExpr(..) , constNum - , Function(..) -- * Assignment , Assign(..) , assignReg |