Rename remaining modules

1 files changed, 12 insertions, 12 deletions

diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index d88f885..baed3c5 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.Verilog
+Module      : VeriFuzz.Verilog
 Description : The main verilog module with the syntax and code generation.
 Copyright   : (c) 2018-2019, Yann Herklotz Grave
 License     : BSD-3
@@ -10,19 +10,19 @@ Portability : POSIX
 The main verilog module with the syntax and code generation.
 -}
 
-module Test.VeriFuzz.Verilog
+module VeriFuzz.Verilog
   ( -- * AST
-    module Test.VeriFuzz.Verilog.AST
+    module VeriFuzz.Verilog.AST
     -- * Code Generation
-  , module Test.VeriFuzz.Verilog.CodeGen
+  , module VeriFuzz.Verilog.CodeGen
     -- * Verilog mutations
-  , module Test.VeriFuzz.Verilog.Mutate
-  , module Test.VeriFuzz.Verilog.Helpers
-  , module Test.VeriFuzz.Verilog.Arbitrary
+  , module VeriFuzz.Verilog.Mutate
+  , module VeriFuzz.Verilog.Helpers
+  , module VeriFuzz.Verilog.Arbitrary
   ) where
 
-import           Test.VeriFuzz.Verilog.Arbitrary
-import           Test.VeriFuzz.Verilog.AST
-import           Test.VeriFuzz.Verilog.CodeGen
-import           Test.VeriFuzz.Verilog.Helpers
-import           Test.VeriFuzz.Verilog.Mutate
+import           VeriFuzz.Verilog.Arbitrary
+import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.CodeGen
+import           VeriFuzz.Verilog.Helpers
+import           VeriFuzz.Verilog.Mutate