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| author | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
| commit | d350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch) | |
| tree | 868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Verilog.hs | |
| parent | 7653f8fd33162b8b166a12e125c988663ec2fe79 (diff) | |
| download | verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip | |
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index e6f8c54..a45922b 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -18,8 +18,6 @@ module VeriFuzz.Verilog , GenVerilog(..) , genSource , getVerilog - , Description(..) - , getDescription -- * Primitives -- ** Identifier , Identifier(..) @@ -69,7 +67,6 @@ module VeriFuzz.Verilog , exprFunc , exprBody , exprStr - , traverseExpr , ConstExpr(..) , constNum , Function(..) @@ -90,7 +87,6 @@ module VeriFuzz.Verilog , statements , stmntBA , stmntNBA - , stmntCA , stmntTask , stmntSysTask , stmntCondExpr |