diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
| commit | d695414e67f9adb7f665602a20a898fa77eba106 (patch) | |
| tree | d22e902e4e34b5c4385f0c863da6e71803903613 /src/VeriFuzz/Verilog.hs | |
| parent | e22a59ad643ac2fe96b0c11208651a6f7a6605b0 (diff) | |
| download | verismith-d695414e67f9adb7f665602a20a898fa77eba106.tar.gz verismith-d695414e67f9adb7f665602a20a898fa77eba106.zip | |
Change Port type to include lower bound
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 19dc607..4d3b82c 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -114,14 +114,9 @@ module VeriFuzz.Verilog -- * Useful Lenses and Traversals , getModule , getSourceId - -- * Arbitrary - , Arb - , arb - , genPositive ) where -import VeriFuzz.Verilog.Arbitrary import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Gen |