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author | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
commit | 4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc (patch) | |
tree | 9b02e1b92f8abf0baf3dc108ab7f4fb8f33e753a /src/VeriFuzz/Verilog.hs | |
parent | 1aaff80235237507572e0fb4be86f34cb1829b68 (diff) | |
parent | 01c2ab3f6a58d416528efce3057e2cf2f1604489 (diff) | |
download | verismith-feature/nondeterminism.tar.gz verismith-feature/nondeterminism.zip |
Merge branch 'master' into HEADfeature/nondeterminism
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
-rw-r--r-- | src/VeriFuzz/Verilog.hs | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs deleted file mode 100644 index 4b5029c..0000000 --- a/src/VeriFuzz/Verilog.hs +++ /dev/null @@ -1,106 +0,0 @@ -{-| -Module : VeriFuzz.Verilog -Description : Verilog implementation with random generation and mutations. -Copyright : (c) 2019, Yann Herklotz Grave -License : GPL-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -Verilog implementation with random generation and mutations. --} - -{-# LANGUAGE QuasiQuotes #-} - -module VeriFuzz.Verilog - ( SourceInfo(..) - , Verilog(..) - , parseVerilog - , GenVerilog(..) - , genSource - -- * Primitives - -- ** Identifier - , Identifier(..) - -- ** Control - , Delay(..) - , Event(..) - -- ** Operators - , BinaryOperator(..) - , UnaryOperator(..) - -- ** Task - , Task(..) - , taskName - , taskExpr - -- ** Left hand side value - , LVal(..) - , regId - , regExprId - , regExpr - , regSizeId - , regSizeRange - , regConc - -- ** Ports - , PortDir(..) - , PortType(..) - , Port(..) - , portType - , portSigned - , portSize - , portName - -- * Expression - , Expr(..) - , ConstExpr(..) - , constToExpr - , exprToConst - , constNum - -- * Assignment - , Assign(..) - , assignReg - , assignDelay - , assignExpr - , ContAssign(..) - , contAssignNetLVal - , contAssignExpr - -- * Statment - , Statement(..) - , statDelay - , statDStat - , statEvent - , statEStat - , statements - , stmntBA - , stmntNBA - , stmntTask - , stmntSysTask - , stmntCondExpr - , stmntCondTrue - , stmntCondFalse - -- * Module - , ModDecl(..) - , modId - , modOutPorts - , modInPorts - , modItems - , ModItem(..) - , modContAssign - , modInstId - , modInstName - , modInstConns - , traverseModItem - , declDir - , declPort - , ModConn(..) - , modConnName - , modExpr - -- * Useful Lenses and Traversals - , getModule - , getSourceId - -- * Quote - , verilog - ) -where - -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Parser -import VeriFuzz.Verilog.Quote |