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authorYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:39:52 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:39:52 +0000
commit1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad (patch)
tree2c9a8d54bf6f9870f0ae62c150803ccec90d46e7 /src/VeriFuzz/Verilog.hs
parenta38289ca9d96e97bc4e65b67c50f5805d56a3d86 (diff)
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-{-|
-Module : VeriFuzz.Verilog
-Description : The main verilog module with the syntax and code generation.
-Copyright : (c) 2018-2019, Yann Herklotz Grave
-License : BSD-3
-Maintainer : ymherklotz [at] gmail [dot] com
-Stability : experimental
-Portability : POSIX
-
-The main verilog module with the syntax and code generation.
--}
-
-module VeriFuzz.Verilog
- ( -- * AST
- module VeriFuzz.Verilog.AST
- -- * Code Generation
- , module VeriFuzz.Verilog.CodeGen
- -- * Verilog mutations
- , module VeriFuzz.Verilog.Mutate
- , module VeriFuzz.Verilog.Helpers
- )
-where
-
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
-import VeriFuzz.Verilog.Helpers
-import VeriFuzz.Verilog.Mutate