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| author | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
| commit | 186bb5f37770c150bd8e601e9761211af6a9c277 (patch) | |
| tree | 33ccc13403d1c9a168909b1e9987f29028834396 /src/VeriFuzz/Verilog/AST.hs | |
| parent | aefb46596f3f2302540a83b2be8b042232822a2f (diff) | |
| download | verismith-186bb5f37770c150bd8e601e9761211af6a9c277.tar.gz verismith-186bb5f37770c150bd8e601e9761211af6a9c277.zip | |
Fix the generation of modules and add initialisation
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 270793d..8ed0254 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -132,6 +132,7 @@ module VeriFuzz.Verilog.AST , traverseModItem , declDir , declPort + , declVal , ModConn(..) , modConn , modConnName @@ -432,6 +433,7 @@ data ModItem = ModCA { _modContAssign :: !ContAssign } | Always !Statement | Decl { _declDir :: !(Maybe PortDir) , _declPort :: !Port + , _declVal :: Maybe ConstExpr } | ParamDecl { _paramDecl :: NonEmpty Parameter } | LocalParamDecl { _localParamDecl :: NonEmpty LocalParam } |