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| author | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:42 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:42 +0100 |
| commit | 6bcdac596fab6e989c999d63ba3f0ad09532989c (patch) | |
| tree | c15aa2fef405ad8b75c274a697058d1064a13e35 /src/VeriFuzz/Verilog/AST.hs | |
| parent | d695414e67f9adb7f665602a20a898fa77eba106 (diff) | |
| download | verismith-6bcdac596fab6e989c999d63ba3f0ad09532989c.tar.gz verismith-6bcdac596fab6e989c999d63ba3f0ad09532989c.zip | |
Add for loop to design
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 8ed0254..007b3b5 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -48,6 +48,7 @@ module VeriFuzz.Verilog.AST , Port(..) , portType , portSigned + , portSizeLower , portSize , portName -- * Expression @@ -351,10 +352,11 @@ data PortType = Wire -- -- This is now implemented inside 'ModDecl' itself, which uses a list of output -- and input ports. -data Port = Port { _portType :: !PortType - , _portSigned :: !Bool - , _portSize :: {-# UNPACK #-} !Int - , _portName :: {-# UNPACK #-} !Identifier +data Port = Port { _portType :: !PortType + , _portSigned :: !Bool + , _portSizeLower :: {-# UNPACK #-} !Int + , _portSize :: {-# UNPACK #-} !Int + , _portName :: {-# UNPACK #-} !Identifier } deriving (Eq, Show, Ord, Data) -- | This is currently a type because direct module declaration should also be |