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| author | Yann Herklotz <git@yannherklotz.com> | 2019-05-21 20:51:20 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-21 20:58:20 +0100 |
| commit | e8915d759c1f6da2a1f3e8328708f40c2d203022 (patch) | |
| tree | 2773d6ccdb527e133df909d5f35474a80301e2d0 /src/VeriFuzz/Verilog/AST.hs | |
| parent | e2cb5d2cfe050ff45fba823c88a5fa45d3fb556e (diff) | |
| download | verismith-e8915d759c1f6da2a1f3e8328708f40c2d203022.tar.gz verismith-e8915d759c1f6da2a1f3e8328708f40c2d203022.zip | |
Add necessary exports to AST and CodeGen
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 306366c..7a654fd 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -492,7 +492,7 @@ newtype Verilog = Verilog { getVerilog :: [ModDecl] } data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text , _infoSrc :: !Verilog } - deriving (Eq, Show) + deriving (Eq, Ord, Data, Show) $(makeLenses ''Expr) $(makeLenses ''ConstExpr) |