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| author | Yann Herklotz <git@ymhg.org> | 2019-04-09 17:32:11 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 17:32:11 +0100 |
| commit | aefb46596f3f2302540a83b2be8b042232822a2f (patch) | |
| tree | 38afcf0c16635e386fff37c496e1ff5740718cb0 /src/VeriFuzz/Verilog/AST.hs | |
| parent | c1a832419a28ac074cbccbeb7060afd22c36d033 (diff) | |
| download | verismith-aefb46596f3f2302540a83b2be8b042232822a2f.tar.gz verismith-aefb46596f3f2302540a83b2be8b042232822a2f.zip | |
Add probabilities to generation of expressions
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index f84eddf..270793d 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -211,7 +211,7 @@ data UnaryOperator = UnPlus -- ^ @+@ deriving (Eq, Show, Ord, Data) data Function = SignedFunc - | UnSignedFunc + | UnsignedFunc deriving (Eq, Show, Ord, Data) -- | Verilog expression, which can either be a primary expression, unary |