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author | Yann Herklotz <git@ymhg.org> | 2019-05-09 18:54:43 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-05-09 18:54:43 +0100 |
commit | 76ce30d979686307babe8ebb6269072338f24910 (patch) | |
tree | f93ec5dfbd1ffa910f2082cc6772431a8384edda /src/VeriFuzz/Verilog/AST.hs | |
parent | 110d1392882cff9618997acad85af78017688c86 (diff) | |
download | verismith-76ce30d979686307babe8ebb6269072338f24910.tar.gz verismith-76ce30d979686307babe8ebb6269072338f24910.zip |
Add reduction strategy for modules
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index ea7ef1b..c4d889b 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -23,6 +23,8 @@ Defines the types to build a Verilog AST. module VeriFuzz.Verilog.AST ( -- * Top level types SourceInfo(..) + , infoTop + , infoSrc , Verilog(..) -- * Primitives -- ** Identifier @@ -455,11 +457,11 @@ traverseModItem f (ModInst a b e) = traverseModItem _ e = pure e -- | The complete sourcetext for the Verilog module. -newtype Verilog = Verilog { _getVerilog :: [ModDecl] } +newtype Verilog = Verilog { getVerilog :: [ModDecl] } deriving (Eq, Show, Ord, Data, Semigroup, Monoid) -data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text - , runSource :: !Verilog +data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text + , _infoSrc :: !Verilog } deriving (Eq, Show) @@ -477,6 +479,7 @@ $(makeLenses ''ModItem) $(makeLenses ''Parameter) $(makeLenses ''LocalParam) $(makeLenses ''ModDecl) +$(makeLenses ''SourceInfo) $(makeWrapped ''Verilog) $(makeWrapped ''Identifier) $(makeWrapped ''Delay) |