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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:13 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:17 +0000 |
commit | 99fe59abc997ba6f65896a2377881409e257faf9 (patch) | |
tree | b83a36efac0fd0fcdd3838f3321428d6bd2de6e3 /src/VeriFuzz/Verilog/AST.hs | |
parent | 64a0ae3600073f486462b1d056409954634b0084 (diff) | |
download | verismith-99fe59abc997ba6f65896a2377881409e257faf9.tar.gz verismith-99fe59abc997ba6f65896a2377881409e257faf9.zip |
Rename moduleId to modId
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index b3754ec..f940281 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -91,7 +91,7 @@ module VeriFuzz.Verilog.AST , stmntSysTask -- * Module , ModDecl(..) - , moduleId + , modId , modOutPorts , modInPorts , modItems @@ -495,7 +495,7 @@ instance QC.Arbitrary ModItem where ] -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' -data ModDecl = ModDecl { _moduleId :: Identifier +data ModDecl = ModDecl { _modId :: Identifier , _modOutPorts :: [Port] , _modInPorts :: [Port] , _modItems :: [ModItem] |