diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-15 19:50:49 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-15 19:50:49 +0100 |
| commit | 705bdb142b1088676ddc3178d8677bd40ab2b1d6 (patch) | |
| tree | 74ad534cb5bb6b5156f8b468a149263ece2bdda5 /src/VeriFuzz/Verilog/BitVec.hs | |
| parent | 398aefd8a90e8f7ade6958ccd8e006308fbf1410 (diff) | |
| download | verismith-705bdb142b1088676ddc3178d8677bd40ab2b1d6.tar.gz verismith-705bdb142b1088676ddc3178d8677bd40ab2b1d6.zip | |
Format with brittany and add right modules
Diffstat (limited to 'src/VeriFuzz/Verilog/BitVec.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/BitVec.hs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs index 436af7b..cdae0f7 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/VeriFuzz/Verilog/BitVec.hs @@ -104,12 +104,12 @@ rotateBitVec b@(BitVec s _) n | n >= 0 = iterate rotateL1 b !! n testBits a b' n' = if testBit n' a then bit b' else zeroBits width' :: Integer -> Int -width' a | a == 0 = 1 +width' a | a == 0 = 1 | otherwise = width'' a - where - width'' a' | a' == 0 = 0 - | a' == -1 = 1 - | otherwise = 1 + width'' (shiftR a' 1) + where + width'' a' | a' == 0 = 0 + | a' == -1 = 1 + | otherwise = 1 + width'' (shiftR a' 1) both :: (a -> b) -> (a, a) -> (b, b) both f (a, b) = (f a, f b) |