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| author | Yann Herklotz <git@ymhg.org> | 2019-05-09 18:54:43 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-09 18:54:43 +0100 |
| commit | 76ce30d979686307babe8ebb6269072338f24910 (patch) | |
| tree | f93ec5dfbd1ffa910f2082cc6772431a8384edda /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 110d1392882cff9618997acad85af78017688c86 (diff) | |
| download | verismith-76ce30d979686307babe8ebb6269072338f24910.tar.gz verismith-76ce30d979686307babe8ebb6269072338f24910.zip | |
Add reduction strategy for modules
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index f20d959..2531519 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -55,7 +55,7 @@ moduleDecl (ModDecl i outP inP items ps) = <> ports <> ";\n" <> modI - <> "endmodule\n" + <> "endmodule\n\n" where ports | null outP && null inP = "" | otherwise = "(" <> comma (modPort <$> outIn) <> ")" |