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| author | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
| commit | 30fbe26f59e54a276f88650ffa5e78343b5411eb (patch) | |
| tree | aa3166c423f262ee6296826d2c815a0b54084c31 /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | b5c035e45949945cc62845fa6492cffa77992524 (diff) | |
| parent | c19a51a8156bbcaee13d9819c8fe54ed0ca5c4cc (diff) | |
| download | verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.tar.gz verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.zip | |
Merge branch 'master' into fix/resize-modports
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index a0ec0cc..82945aa 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -17,18 +17,20 @@ This module generates the code from the Verilog AST defined in module VeriFuzz.Verilog.CodeGen ( -- * Code Generation GenVerilog(..) - , genSource + , Source(..) , render ) where -import Data.Data (Data) -import Data.List.NonEmpty (NonEmpty (..), toList) -import Data.Text (Text) -import qualified Data.Text as T +import Data.Data ( Data ) +import Data.List.NonEmpty ( NonEmpty(..) + , toList + ) +import Data.Text ( Text ) +import qualified Data.Text as T import Data.Text.Prettyprint.Doc -import Numeric (showHex) -import VeriFuzz.Internal hiding (comma) +import Numeric ( showHex ) +import VeriFuzz.Internal hiding ( comma ) import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec |