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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:23:05 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:23:05 +0000 |
| commit | 3c335483aebf2a34368642d9b36e5d4cc1b554f5 (patch) | |
| tree | 9c2e043cf49fe8e3bb32124e62af2d91a9a1b665 /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | ed10d3ad5edcc5b302395ac74d06bffe05446e87 (diff) | |
| download | verismith-3c335483aebf2a34368642d9b36e5d4cc1b554f5.tar.gz verismith-3c335483aebf2a34368642d9b36e5d4cc1b554f5.zip | |
Fix warnings
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 8dc74a0..acbf15b 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -59,13 +59,13 @@ genModuleDecl :: ModDecl -> Text genModuleDecl mod = "module " <> mod ^. moduleId . getIdentifier <> ports <> ";\n" - <> modItems + <> modI <> "endmodule\n" where ports | noIn && noOut = "" | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" - modItems = fold $ genModuleItem <$> mod ^. moduleItems + modI = fold $ genModuleItem <$> mod ^. modItems noOut = null $ mod ^. modOutPorts noIn = null $ mod ^. modInPorts outIn = (mod ^. modOutPorts) ++ (mod ^. modInPorts) |