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| author | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:32 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:56 +0100 |
| commit | 1f92f329dabfaf5077bed677a273a196667229e1 (patch) | |
| tree | a19c9ed6ec91db71d51684911420fd12a80a59bc /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 1486a2afa481de46938c1bc122c469975978593f (diff) | |
| download | verismith-1f92f329dabfaf5077bed677a273a196667229e1.tar.gz verismith-1f92f329dabfaf5077bed677a273a196667229e1.zip | |
Add random bit selection for wires
This has not been tested fully yet
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 09d6d6f..2cd2b13 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -138,6 +138,8 @@ expr (BinOp eRhs bin eLhs) = "(" <> expr eRhs <> binaryOp bin <> expr eLhs <> ")" expr (Number b ) = showNum b expr (Id i ) = getIdentifier i +expr (VecSelect i e) = getIdentifier i <> "[" <> genExpr e <> "]" +expr (RangeSelect i r) = getIdentifier i <> range r expr (Concat c ) = "{" <> comma (expr <$> c) <> "}" expr (UnOp u e ) = "(" <> unaryOp u <> expr e <> ")" expr (Cond l t f) = "(" <> expr l <> " ? " <> expr t <> " : " <> expr f <> ")" |