diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 17:46:56 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 17:46:56 +0000 |
| commit | 3e37e75f804cbf6b5ce04a427888fb0f0859660a (patch) | |
| tree | e0602c9777a36ad677009031cc8edaa5fefc22cd /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 8a70b3fa892aaa095aa423609bfadaecea44c655 (diff) | |
| download | verismith-3e37e75f804cbf6b5ce04a427888fb0f0859660a.tar.gz verismith-3e37e75f804cbf6b5ce04a427888fb0f0859660a.zip | |
[Fix #22] Fix SAT solver equivalence checking
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 0b7f422..8b574c2 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -86,12 +86,18 @@ genPortDir PortInOut = "inout" genModuleItem :: ModItem -> Text genModuleItem (ModCA ca) = genContAssign ca genModuleItem (ModInst (Identifier i) (Identifier name) conn) = - i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" + i <> " " <> name <> "(" <> comma (genModConn <$> conn) <> ")" <> ";\n" genModuleItem (Initial stat ) = "initial " <> genStmnt stat genModuleItem (Always stat ) = "always " <> genStmnt stat genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n" where makePort = (<> " ") . genPortDir +genModConn :: ModConn -> Text +genModConn (ModConn c) = + genExpr c +genModConn (ModConnNamed n c) = + "." <> n ^. getIdentifier <> "(" <> genExpr c <> ")" + -- | Generate continuous assignment genContAssign :: ContAssign -> Text genContAssign (ContAssign val e) = "assign " <> name <> " = " <> expr <> ";\n" |