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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:13 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:17 +0000 |
| commit | 99fe59abc997ba6f65896a2377881409e257faf9 (patch) | |
| tree | b83a36efac0fd0fcdd3838f3321428d6bd2de6e3 /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 64a0ae3600073f486462b1d056409954634b0084 (diff) | |
| download | verismith-99fe59abc997ba6f65896a2377881409e257faf9.tar.gz verismith-99fe59abc997ba6f65896a2377881409e257faf9.zip | |
Rename moduleId to modId
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 956472f..58b1d16 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -53,7 +53,7 @@ genDescription desc = genModuleDecl $ desc ^. getDescription -- | Generate the 'ModDecl' for a module and convert it to 'Text'. genModuleDecl :: ModDecl -> Text genModuleDecl m = - "module " <> m ^. moduleId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n" + "module " <> m ^. modId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n" where ports | noIn && noOut = "" | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" |