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authorYann Herklotz <git@yannherklotz.com>2019-07-21 13:37:25 +0200
committerYann Herklotz <git@yannherklotz.com>2019-07-21 13:37:25 +0200
commit30fbe26f59e54a276f88650ffa5e78343b5411eb (patch)
treeaa3166c423f262ee6296826d2c815a0b54084c31 /src/VeriFuzz/Verilog/Eval.hs
parentb5c035e45949945cc62845fa6492cffa77992524 (diff)
parentc19a51a8156bbcaee13d9819c8fe54ed0ca5c4cc (diff)
downloadverismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.tar.gz
verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.zip
Merge branch 'master' into fix/resize-modports
Diffstat (limited to 'src/VeriFuzz/Verilog/Eval.hs')
-rw-r--r--src/VeriFuzz/Verilog/Eval.hs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs
index 4a43c19..d8840e3 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriFuzz/Verilog/Eval.hs
@@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval
where
import Data.Bits
-import Data.Foldable (fold)
-import Data.Functor.Foldable hiding (fold)
-import Data.Maybe (listToMaybe)
+import Data.Foldable ( fold )
+import Data.Functor.Foldable hiding ( fold )
+import Data.Maybe ( listToMaybe )
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec