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authorYann Herklotz <git@ymhg.org>2019-04-03 19:53:56 +0100
committerYann Herklotz <git@ymhg.org>2019-04-03 19:53:56 +0100
commit31325e890e8a7807ec5a3d996c3789baad0e8dc4 (patch)
treec3df20e33ff945c1ec10fc132ff7a12127176703 /src/VeriFuzz/Verilog/Gen.hs
parent6776d38b11186e97101995eb2c071096cc1d648b (diff)
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Generate Verilog instead of ModDecl
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