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author | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
commit | 4b5401ef3400413be0559dfa17718611822fc4c6 (patch) | |
tree | f57cd74848f1f07454724e1d49369e6847f50ae7 /src/VeriFuzz/Verilog/Gen.hs | |
parent | 310171c8891b61958c10a701f4837db3238582a8 (diff) | |
download | verismith-4b5401ef3400413be0559dfa17718611822fc4c6.tar.gz verismith-4b5401ef3400413be0559dfa17718611822fc4c6.zip |
Generate flip-flops instead of latches
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 1793582..87a0a31 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -105,13 +105,6 @@ newPort pt = do choose :: PortType -> Port -> Bool choose ptype (Port a _ _ _) = ptype == a -select :: PortType -> StateGen Port -select ptype = do - context <- get - case filter (choose Reg) $ context ^.. variables . traverse of - [] -> newPort ptype - l -> Hog.element l - scopedExpr :: StateGen Expr scopedExpr = do context <- get @@ -166,9 +159,8 @@ statement = do always :: StateGen ModItem always = do - stat <- SeqBlock <$> some statement - eventReg <- select Reg - return $ Always (EventCtrl (EId (eventReg ^. portName)) (Just stat)) + stat <- SeqBlock <$> some statement + return $ Always (EventCtrl (EPosEdge "clk") (Just stat)) -- | Generate a random module item. modItem :: StateGen ModItem @@ -204,9 +196,10 @@ moduleDef top = do initBlock <- initialBlock let local = filter (`notElem` portList) $ context ^. variables let size = sum $ local ^.. traverse . portSize + let clock = Port Wire False 1 "clk" let yport = Port Wire False size "y" let comb = combineAssigns_ yport local - return . declareMod local . ModDecl name [yport] portList $ initBlock : mi <> [comb] + return . declareMod local . ModDecl name [yport] (clock:portList) $ initBlock : mi <> [comb] -- | Procedural generation method for random Verilog. Uses internal 'Reader' and -- 'State' to keep track of the current Verilog code structure. |