diff options
| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 12:55:19 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 12:55:19 +0100 |
| commit | 58eb1aea52fb57666f2f4e620e3ac9a8dd05522c (patch) | |
| tree | 96ad46284a27663d28e13298595f31531bfb68f1 /src/VeriFuzz/Verilog/Gen.hs | |
| parent | 12a74a1841ffb5842af029ffcce77c3e765e00f8 (diff) | |
| download | verismith-58eb1aea52fb57666f2f4e620e3ac9a8dd05522c.tar.gz verismith-58eb1aea52fb57666f2f4e620e3ac9a8dd05522c.zip | |
Add XOR to the output
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index bc40de5..828224f 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -464,7 +464,7 @@ moduleDef top = do ^.. traverse . portSize let clock = Port Wire False 1 "clk" - let yport = Port Wire False size "y" + let yport = Port Wire False 1 "y" let comb = combineAssigns_ yport local return . declareMod local |