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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 12:06:49 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 12:06:49 +0100 |
| commit | c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63 (patch) | |
| tree | 3e3bb7026ba268eed2f842d702195b0472c905d2 /src/VeriFuzz/Verilog/Gen.hs | |
| parent | e4737c37c9dc358d56dbb7a97d68de2c93053c0c (diff) | |
| download | verismith-c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63.tar.gz verismith-c40faa081ae7f31cb1b6125d1c5c3bdf650f3f63.zip | |
Add combination option
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index c903e28..cb3a8ad 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -455,6 +455,7 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get + config <- lift ask let local = filter (`notElem` portList) $ _variables context let size = @@ -465,7 +466,7 @@ moduleDef top = do . portSize let clock = Port Wire False 1 "clk" let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ yport local + let comb = combineAssigns_ (config ^. configProperty . propCombine) yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) |