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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:20 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:27 +0100 |
| commit | 720fa7a822a077458cf0b29e9dcdc754a881e8bd (patch) | |
| tree | fa00db795c17bba78b02de2823c1092fae1d81ec /src/VeriFuzz/Verilog/Gen.hs | |
| parent | f3268d934a9a2b01633b5f7a3353d1a97c40a9df (diff) | |
| download | verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.tar.gz verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.zip | |
Format all files
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index c8860ce..e52a158 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -455,7 +455,7 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get - config <- lift ask + config <- lift ask let local = filter (`notElem` portList) $ _variables context let size = @@ -465,9 +465,10 @@ moduleDef top = do ^.. traverse . portSize let combine = config ^. configProperty . propCombine - let clock = Port Wire False 1 "clk" - let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ combine yport local + let clock = Port Wire False 1 "clk" + let yport = + if combine then Port Wire False 1 "y" else Port Wire False size "y" + let comb = combineAssigns_ combine yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) |