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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 19:39:52 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 19:39:52 +0000 |
commit | 1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad (patch) | |
tree | 2c9a8d54bf6f9870f0ae62c150803ccec90d46e7 /src/VeriFuzz/Verilog/Helpers.hs | |
parent | a38289ca9d96e97bc4e65b67c50f5805d56a3d86 (diff) | |
download | verismith-1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad.tar.gz verismith-1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad.zip |
More restructuring
Diffstat (limited to 'src/VeriFuzz/Verilog/Helpers.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/Helpers.hs | 72 |
1 files changed, 0 insertions, 72 deletions
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs deleted file mode 100644 index 99e5f38..0000000 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ /dev/null @@ -1,72 +0,0 @@ -{-| -Module : VeriFuzz.Verilog.Helpers -Description : Defaults and common functions. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Defaults and common functions. --} - -module VeriFuzz.Verilog.Helpers where - -import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST - -regDecl :: Identifier -> ModItem -regDecl = Decl Nothing . Port (Reg False) 1 - -wireDecl :: Identifier -> ModItem -wireDecl = Decl Nothing . Port Wire 1 - --- | Create an empty module. -emptyMod :: ModDecl -emptyMod = ModDecl "" [] [] [] - --- | Set a module name for a module declaration. -setModName :: Text -> ModDecl -> ModDecl -setModName str = modId .~ Identifier str - --- | Add a input port to the module declaration. -addModPort :: Port -> ModDecl -> ModDecl -addModPort port = modInPorts %~ (:) port - -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc - -testBench :: ModDecl -testBench = ModDecl - "main" - [] - [] - [ regDecl "a" - , regDecl "b" - , wireDecl "c" - , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] - , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 - -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" - -- [ Str "%d & %d = %d" - -- , PrimExpr $ PrimId "a" - -- , PrimExpr $ PrimId "b" - -- , PrimExpr $ PrimId "c" - -- ] - -- , SysTaskEnable $ Task "finish" [] - ] - ] - -addTestBench :: VerilogSrc -> VerilogSrc -addTestBench = addDescription $ Description testBench - -defaultPort :: Identifier -> Port -defaultPort = Port Wire 1 - -portToExpr :: Port -> Expr -portToExpr (Port _ _ i) = Id i - -modName :: ModDecl -> Text -modName = view $ modId . getIdentifier |