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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:20:33 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:20:33 +0000 |
| commit | 4ba440d842e9a0502b429fbc04e2be41c8037a4c (patch) | |
| tree | fb6440ebe2905b4c2c820dece67ef430d92731af /src/VeriFuzz/Verilog/Helpers.hs | |
| parent | 708e0b680a48e6eb21664a5f1de21815bebf91d2 (diff) | |
| download | verismith-4ba440d842e9a0502b429fbc04e2be41c8037a4c.tar.gz verismith-4ba440d842e9a0502b429fbc04e2be41c8037a4c.zip | |
Add brittany formatting instead of stylish-haskell
Diffstat (limited to 'src/VeriFuzz/Verilog/Helpers.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Helpers.hs | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index 554b8ba..53d219b 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -13,7 +13,7 @@ Defaults and common functions. module VeriFuzz.Verilog.Helpers where import Control.Lens -import Data.Text (Text) +import Data.Text ( Text ) import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem @@ -38,16 +38,16 @@ addDescription :: Description -> VerilogSrc -> VerilogSrc addDescription desc = getVerilogSrc %~ (:) desc testBench :: ModDecl -testBench = - ModDecl "main" [] [] +testBench = ModDecl + "main" + [] + [] [ regDecl "a" , regDecl "b" , wireDecl "c" - , ModInst "and" "and_gate" - [ ModConn $ Id "c" - , ModConn $ Id "a" - , ModConn $ Id "b" - ] + , ModInst "and" + "and_gate" + [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] , Initial $ SeqBlock [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 |