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| author | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
| commit | 186bb5f37770c150bd8e601e9761211af6a9c277 (patch) | |
| tree | 33ccc13403d1c9a168909b1e9987f29028834396 /src/VeriFuzz/Verilog/Internal.hs | |
| parent | aefb46596f3f2302540a83b2be8b042232822a2f (diff) | |
| download | verismith-186bb5f37770c150bd8e601e9761211af6a9c277.tar.gz verismith-186bb5f37770c150bd8e601e9761211af6a9c277.zip | |
Fix the generation of modules and add initialisation
Diffstat (limited to 'src/VeriFuzz/Verilog/Internal.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Internal.hs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index a7b0a15..d68e46c 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -33,10 +33,10 @@ import Data.Text (Text) import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem -regDecl = Decl Nothing . Port Reg False 1 +regDecl i = Decl Nothing (Port Reg False 1 i) Nothing wireDecl :: Identifier -> ModItem -wireDecl = Decl Nothing . Port Wire False 1 +wireDecl i = Decl Nothing (Port Wire False 1 i) Nothing -- | Create an empty module. emptyMod :: ModDecl @@ -75,7 +75,8 @@ testBench = ModDecl -- ] -- , SysTaskEnable $ Task "finish" [] ] - ] [] + ] + [] addTestBench :: Verilog -> Verilog addTestBench = addModDecl testBench |