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authorYann Herklotz <git@yannherklotz.com>2019-07-21 13:37:25 +0200
committerYann Herklotz <git@yannherklotz.com>2019-07-21 13:37:25 +0200
commit30fbe26f59e54a276f88650ffa5e78343b5411eb (patch)
treeaa3166c423f262ee6296826d2c815a0b54084c31 /src/VeriFuzz/Verilog/Internal.hs
parentb5c035e45949945cc62845fa6492cffa77992524 (diff)
parentc19a51a8156bbcaee13d9819c8fe54ed0ca5c4cc (diff)
downloadverismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.tar.gz
verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.zip
Merge branch 'master' into fix/resize-modports
Diffstat (limited to 'src/VeriFuzz/Verilog/Internal.hs')
-rw-r--r--src/VeriFuzz/Verilog/Internal.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 8d19c14..16148cf 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal
where
import Control.Lens
-import Data.Text (Text)
+import Data.Text ( Text )
import VeriFuzz.Verilog.AST
regDecl :: Identifier -> ModItem