diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
| commit | d350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch) | |
| tree | 868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Verilog/Internal.hs | |
| parent | 7653f8fd33162b8b166a12e125c988663ec2fe79 (diff) | |
| download | verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip | |
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Verilog/Internal.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Internal.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 5999a31..a7b0a15 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -16,7 +16,7 @@ module VeriFuzz.Verilog.Internal , emptyMod , setModName , addModPort - , addDescription + , addModDecl , testBench , addTestBench , defaultPort @@ -40,7 +40,7 @@ wireDecl = Decl Nothing . Port Wire False 1 -- | Create an empty module. emptyMod :: ModDecl -emptyMod = ModDecl "" [] [] [] +emptyMod = ModDecl "" [] [] [] [] -- | Set a module name for a module declaration. setModName :: Text -> ModDecl -> ModDecl @@ -50,8 +50,8 @@ setModName str = modId .~ Identifier str addModPort :: Port -> ModDecl -> ModDecl addModPort port = modInPorts %~ (:) port -addDescription :: Description -> Verilog -> Verilog -addDescription desc = getVerilog %~ (:) desc +addModDecl :: ModDecl -> Verilog -> Verilog +addModDecl desc = getVerilog %~ (:) desc testBench :: ModDecl testBench = ModDecl @@ -75,10 +75,10 @@ testBench = ModDecl -- ] -- , SysTaskEnable $ Task "finish" [] ] - ] + ] [] addTestBench :: Verilog -> Verilog -addTestBench = addDescription $ Description testBench +addTestBench = addModDecl testBench defaultPort :: Identifier -> Port defaultPort = Port Wire False 1 |