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author | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
commit | cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (patch) | |
tree | f00baaec9dcb747c27375af366ad9aec9d2dbe16 /src/VeriFuzz/Verilog/Internal.hs | |
parent | 74a14ef30359e653259bf7139fe806548edefd14 (diff) | |
download | verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.tar.gz verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.zip |
Change name from VeriFuzz to VeriSmith
Diffstat (limited to 'src/VeriFuzz/Verilog/Internal.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/Internal.hs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 42eb4e2..ed91b12 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Internal +Module : VeriSmith.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Defaults and common functions. -} -module VeriFuzz.Verilog.Internal +module VeriSmith.Verilog.Internal ( regDecl , wireDecl , emptyMod @@ -29,8 +29,8 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST +import Data.Text (Text) +import VeriSmith.Verilog.AST regDecl :: Identifier -> ModItem regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing |