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| author | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:42:03 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:42:03 +0100 |
| commit | 52fd1a61b5491b877cd36123805144e5a635bda5 (patch) | |
| tree | 31278d3d440ae2ed1d72810af74fa2788e185e81 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 1bf5b56da8df267fd33e738b53e29e832854856b (diff) | |
| download | verismith-52fd1a61b5491b877cd36123805144e5a635bda5.tar.gz verismith-52fd1a61b5491b877cd36123805144e5a635bda5.zip | |
Fix some of the doctests in Mutate.hs
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index e7b4874..35e0458 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -118,9 +118,9 @@ allVars m = -- -- >>> render $ instantiateMod m main -- module main; --- wire [(3'h4):(1'h0)] y; --- reg [(3'h4):(1'h0)] x; --- m m1(y, x); +-- wire [(3'h4):(1'h0)] y; +-- reg [(3'h4):(1'h0)] x; +-- m m1(y, x); -- endmodule -- <BLANKLINE> -- <BLANKLINE> @@ -181,8 +181,8 @@ filterChar t ids = -- -- >>> GenVerilog $ initMod m -- module m(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> |