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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 12:55:19 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-02 12:55:19 +0100 |
| commit | 58eb1aea52fb57666f2f4e620e3ac9a8dd05522c (patch) | |
| tree | 96ad46284a27663d28e13298595f31531bfb68f1 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 12a74a1841ffb5842af029ffcce77c3e765e00f8 (diff) | |
| download | verismith-58eb1aea52fb57666f2f4e620e3ac9a8dd05522c.tar.gz verismith-58eb1aea52fb57666f2f4e620e3ac9a8dd05522c.zip | |
Add XOR to the output
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 66f3c37..8af0182 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -377,13 +377,14 @@ removeId i = transform trans combineAssigns :: Port -> [ModItem] -> [ModItem] combineAssigns p a = - a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns] + a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal combineAssigns_ :: Port -> [Port] -> ModItem combineAssigns_ p ps = ModCA . ContAssign (p ^. portName) + . UnOp UnXor . fold $ Id <$> ps |