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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:56:58 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:57:18 +0000 |
| commit | 983669aa390c4cc1aaf6e4bee914d1a7de9a58e4 (patch) | |
| tree | e02cd385806eb6d234858c94a83870f49a30e584 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 23800af41dc2b6c4e430c143024d9ec5804f2c08 (diff) | |
| download | verismith-983669aa390c4cc1aaf6e4bee914d1a7de9a58e4.tar.gz verismith-983669aa390c4cc1aaf6e4bee914d1a7de9a58e4.zip | |
Fix all the warnings
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index dea5a66..eddb93a 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -139,10 +139,10 @@ makeIdFrom a i = -- modules to instantiate. makeTop :: Int -> ModDecl -> ModDecl makeTop i m = - ModDecl (m ^. moduleId) ys (m ^. modInPorts) modItems + ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt where ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1..i] - modItems = instantiateMod_ . modN <$> [1..i] + modIt = instantiateMod_ . modN <$> [1..i] modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] |