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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:13 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:17 +0000 |
| commit | 99fe59abc997ba6f65896a2377881409e257faf9 (patch) | |
| tree | b83a36efac0fd0fcdd3838f3321428d6bd2de6e3 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 64a0ae3600073f486462b1d056409954634b0084 (diff) | |
| download | verismith-99fe59abc997ba6f65896a2377881409e257faf9.tar.gz verismith-99fe59abc997ba6f65896a2377881409e257faf9.zip | |
Rename moduleId to modId
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 82d3db9..dca0dd9 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -92,8 +92,8 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++) where out = Decl Nothing <$> m ^. modOutPorts regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg False) - inst = ModInst (m ^. moduleId) (m ^. moduleId <> (Identifier . showT $ count + 1)) conns - count = length . filter (== m ^. moduleId) $ main ^.. modItems . traverse . modInstId + inst = ModInst (m ^. modId) (m ^. modId <> (Identifier . showT $ count + 1)) conns + count = length . filter (== m ^. modId) $ main ^.. modItems . traverse . modInstId conns = ModConn . Id <$> allVars m -- | Instantiate without adding wire declarations. It also does not count the @@ -103,7 +103,7 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++) -- m m(y, x); -- <BLANKLINE> instantiateMod_ :: ModDecl -> ModItem -instantiateMod_ m = ModInst (m ^. moduleId) (m ^. moduleId) conns +instantiateMod_ m = ModInst (m ^. modId) (m ^. modId) conns where conns = ModConn @@ -131,8 +131,8 @@ makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a -- | Make top level module for equivalence verification. Also takes in how many -- modules to instantiate. makeTop :: Int -> ModDecl -> ModDecl -makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt +makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt where ys = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i] modIt = instantiateMod_ . modN <$> [1 .. i] - modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] + modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] |