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| author | Yann Herklotz <git@ymhg.org> | 2019-04-13 12:21:05 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-13 12:21:05 +0100 |
| commit | b281cee59daa51ba4607229092274dfa2f801806 (patch) | |
| tree | 5b8b232f593e4c2d14aaa93ea5856231f12f8623 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 79a6b80ada570123e85590d484a72c810d4d8d0c (diff) | |
| download | verismith-b281cee59daa51ba4607229092274dfa2f801806.tar.gz verismith-b281cee59daa51ba4607229092274dfa2f801806.zip | |
Fix tests passing
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index f4330bc..536ebef 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -107,7 +107,7 @@ allVars m = -- $setup -- >>> import VeriFuzz.Verilog.CodeGen --- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] []) +-- >>> let m = (ModDecl (Identifier "m") [Port Wire False 0 5 (Identifier "y")] [Port Wire False 0 5 "x"] [] []) -- >>> let main = (ModDecl "main" [] [] [] []) -- | Add a Module Instantiation using 'ModInst' from the first module passed to |