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| author | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:32 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:56 +0100 |
| commit | 1f92f329dabfaf5077bed677a273a196667229e1 (patch) | |
| tree | a19c9ed6ec91db71d51684911420fd12a80a59bc /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 1486a2afa481de46938c1bc122c469975978593f (diff) | |
| download | verismith-1f92f329dabfaf5077bed677a273a196667229e1.tar.gz verismith-1f92f329dabfaf5077bed677a273a196667229e1.zip | |
Add random bit selection for wires
This has not been tested fully yet
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 39a136e..7b93633 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -33,6 +33,7 @@ module VeriFuzz.Verilog.Mutate , combineAssigns , combineAssigns_ , declareMod + , fromPort ) where @@ -284,3 +285,6 @@ combineAssigns_ p ps = <$> ps ^.. traverse . portName + +fromPort :: Port -> Identifier +fromPort (Port _ _ _ i) = i |