diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 16:49:17 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 16:49:17 +0000 |
| commit | d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b (patch) | |
| tree | 981c9443c8d919b0bc58abbfb8d617223eb99a9f /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 8cfacbac3bb16fc0294e6eaf7c7b16c238c58d73 (diff) | |
| download | verismith-d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b.tar.gz verismith-d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b.zip | |
Prettify files
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index dca0dd9..0e68419 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -136,3 +136,10 @@ makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt ys = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i] modIt = instantiateMod_ . modN <$> [1 .. i] modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] + +makeTopAssert :: ModDecl -> ModDecl +makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ ((Port Wire 1 "clk") :)) . makeTop 2 + where + assert = Always . EventCtrl e . Just $ SeqBlock + [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] + e = EPosEdge "clk" |