diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 11:38:19 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 11:38:19 +0000 |
| commit | e6976ea66dad180203e1e0f678ac56c515a6878a (patch) | |
| tree | d6cd8cf307be8b8d68b74fefa43f2941352d498b /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | d2e9c2d9395f613de8237bcf6ec5005c1144f781 (diff) | |
| download | verismith-e6976ea66dad180203e1e0f678ac56c515a6878a.tar.gz verismith-e6976ea66dad180203e1e0f678ac56c515a6878a.zip | |
Make code a bit more readable
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 7e000e1..2865ff0 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -159,8 +159,9 @@ makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] makeTopAssert :: ModDecl -> ModDecl -makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ ((Port Wire 1 "clk") :)) . makeTop 2 +makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2 where assert = Always . EventCtrl e . Just $ SeqBlock [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] e = EPosEdge "clk" + addClk = ((Port Wire 1 "clk") :) |