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authorYann Herklotz <ymherklotz@gmail.com>2019-01-10 17:20:42 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-01-10 17:20:42 +0000
commitfa4d1bf03003944e8a73ac4e341633020edca6af (patch)
treeaa2afd8d9fd41430cc1817c45ec618564218056c /src/VeriFuzz/Verilog/Mutate.hs
parente0fecd298f622e8943d6ae2bfc7de00fe36e57a7 (diff)
downloadverismith-fa4d1bf03003944e8a73ac4e341633020edca6af.tar.gz
verismith-fa4d1bf03003944e8a73ac4e341633020edca6af.zip
Fix warnings
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 501d217..36cdb9b 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -107,7 +107,7 @@ instantiateMod mod main =
-- | Instantiate without adding wire declarations. It also does not count the
-- current instantiations of the same module.
--
--- >>> instantiateMod_ mod main
+-- >>> instantiateMod_ mod
-- m m(y, x);
-- <BLANKLINE>
instantiateMod_ :: ModDecl -> ModItem