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| author | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:32:32 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:32:32 +0100 |
| commit | 3f4cc4d325f740f7e70ad8ce02087fca41f79e31 (patch) | |
| tree | 4507bdfbaefdc15bcd9d8628cba0fdc8dee16da9 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | f1da60acb6edc5ba8c6beba1287931e8c47b91ec (diff) | |
| download | verismith-3f4cc4d325f740f7e70ad8ce02087fca41f79e31.tar.gz verismith-3f4cc4d325f740f7e70ad8ce02087fca41f79e31.zip | |
New combine function
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 69b6d57..eca472f 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -31,6 +31,7 @@ module VeriFuzz.Verilog.Mutate , simplify , removeId , combineAssigns + , combineAssigns_ , declareMod ) where @@ -270,3 +271,7 @@ combineAssigns :: Port -> [ModItem] -> [ModItem] combineAssigns p a = a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal + +combineAssigns_ :: Port -> [Port] -> ModItem +combineAssigns_ p ps = + ModCA . ContAssign (p ^. portName) . fold $ Id <$> ps ^.. traverse . portName |