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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
| commit | a27290529940e7a78dfe1d736447ca6f1cf72089 (patch) | |
| tree | 06c52149bbf2216fa02943dae0a4518749a372d0 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b (diff) | |
| download | verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.tar.gz verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.zip | |
Add hlint changes
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 9f22faa..3052598 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -135,6 +135,6 @@ makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a makeTop :: Int -> ModDecl -> ModDecl makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt where - ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1 .. i] + ys = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i] modIt = instantiateMod_ . modN <$> [1 .. i] modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] |