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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:24:10 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 18:24:10 +0000 |
| commit | fed2fb42f5cca17d38ff1ccd948d598dd0616cdc (patch) | |
| tree | db4650c63fd672b1648fd9ebc5b58ae02cbfe42a /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | beb020129a6f5b3fa5ca43274c05b5537731dd72 (diff) | |
| download | verismith-fed2fb42f5cca17d38ff1ccd948d598dd0616cdc.tar.gz verismith-fed2fb42f5cca17d38ff1ccd948d598dd0616cdc.zip | |
Fix documentation error
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 32f0833..dea5a66 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -119,7 +119,7 @@ instantiateMod_ m = -- | Initialise all the inputs and outputs to a module. -- --- >>> render $ initMod mod +-- >>> render $ initMod m -- module m(y, x); -- output wire [4:0] y; -- input wire [4:0] x; |