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authorYann Herklotz <git@ymhg.org>2019-04-12 17:16:24 +0100
committerYann Herklotz <git@ymhg.org>2019-04-12 17:16:24 +0100
commitd695414e67f9adb7f665602a20a898fa77eba106 (patch)
treed22e902e4e34b5c4385f0c863da6e71803903613 /src/VeriFuzz/Verilog/Parser.hs
parente22a59ad643ac2fe96b0c11208651a6f7a6605b0 (diff)
downloadverismith-d695414e67f9adb7f665602a20a898fa77eba106.tar.gz
verismith-d695414e67f9adb7f665602a20a898fa77eba106.zip
Change Port type to include lower bound
Diffstat (limited to 'src/VeriFuzz/Verilog/Parser.hs')
-rw-r--r--src/VeriFuzz/Verilog/Parser.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 3b07366..518bcb9 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -259,7 +259,7 @@ parseNetDecl pd = do
range <- option 1 parseRange
name <- identifier
tok' SymSemi
- return $ Decl pd (Port t sign range name) Nothing
+ return $ Decl pd (Port t sign 0 range name) Nothing
where type_ = tok KWWire $> Wire <|> tok KWReg $> Reg
parsePortDir :: Parser PortDir