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author | Yann Herklotz <git@ymhg.org> | 2019-05-13 14:58:15 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-05-13 14:58:15 +0100 |
commit | 426f0d71eca2dc578e4258df05be296003c3e4cb (patch) | |
tree | fbc3875534155a33ab23c7c34db128ee6fcbf2cf /src/VeriFuzz/Verilog/Parser.hs | |
parent | b5fddf170e4f4d798b0411f417735cec21e20b29 (diff) | |
download | verismith-426f0d71eca2dc578e4258df05be296003c3e4cb.tar.gz verismith-426f0d71eca2dc578e4258df05be296003c3e4cb.zip |
Change the arguments to Text in the Parser
Diffstat (limited to 'src/VeriFuzz/Verilog/Parser.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/Parser.hs | 32 |
1 files changed, 26 insertions, 6 deletions
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index 383a72e..b7840ff 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -14,11 +14,13 @@ whole Verilog syntax, as the AST does not support it either. module VeriFuzz.Verilog.Parser ( -- * Parser parseVerilog - , parseModDecl + , parseVerilogFile + , parseSourceInfoFile -- ** Internal parsers , parseEvent , parseStatement , parseModItem + , parseModDecl , Parser ) where @@ -30,9 +32,13 @@ import Data.Bits import Data.Functor (($>)) import Data.Functor.Identity (Identity) import Data.List (isInfixOf, isPrefixOf, null) +import Data.List.NonEmpty (NonEmpty (..)) +import Data.Text (Text) import qualified Data.Text as T +import qualified Data.Text.IO as T import Text.Parsec hiding (satisfy) import Text.Parsec.Expr +import VeriFuzz.Internal import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec import VeriFuzz.Verilog.Internal @@ -129,10 +135,14 @@ parseFun = do expr <- parens parseExpr return $ Appl (Identifier $ T.pack f) expr +parserNonEmpty :: [a] -> Parser (NonEmpty a) +parserNonEmpty (a:b) = return $ a :| b +parserNonEmpty [] = fail "Concatenation cannot be empty." + parseTerm :: Parser Expr parseTerm = parens parseExpr - <|> (Concat <$> braces (commaSep parseExpr)) + <|> (Concat <$> (braces (commaSep parseExpr) >>= parserNonEmpty)) <|> parseFun <|> parseNum <|> try parseVecSelect @@ -476,9 +486,19 @@ parseVerilogSrc = Verilog <$> many parseModDecl -- | Parse a 'String' containing verilog code. The parser currently only supports -- the subset of Verilog that is being generated randomly. parseVerilog - :: String -- ^ Name of parsed object. - -> String -- ^ Content to be parsed. - -> Either String Verilog -- ^ Returns 'String' with error + :: Text -- ^ Name of parsed object. + -> Text -- ^ Content to be parsed. + -> Either Text Verilog -- ^ Returns 'String' with error -- message if parse fails. parseVerilog s = - bimap show id . parse parseVerilogSrc s . alexScanTokens . preprocess [] s + bimap showT id . parse parseVerilogSrc (T.unpack s) . alexScanTokens . preprocess [] (T.unpack s) . T.unpack + +parseVerilogFile :: Text -> IO Verilog +parseVerilogFile file = do + src <- T.readFile $ T.unpack file + case parseVerilog file src of + Left s -> error $ T.unpack s + Right r -> return r + +parseSourceInfoFile :: Text -> Text -> IO SourceInfo +parseSourceInfoFile top = fmap (SourceInfo top) . parseVerilogFile |