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author | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
commit | d350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch) | |
tree | 868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Verilog/Parser.hs | |
parent | 7653f8fd33162b8b166a12e125c988663ec2fe79 (diff) | |
download | verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip |
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Verilog/Parser.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/Parser.hs | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index a072ce8..1a954fa 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -298,14 +298,12 @@ parseModDecl = do (modPorts PortOut modItem) (modPorts PortIn modItem) modItem - -parseDescription :: Parser Description -parseDescription = Description <$> parseModDecl + [] -- | Parses a 'String' into 'Verilog' by skipping any beginning whitespace -- and then parsing multiple Verilog source. parseVerilogSrc :: Parser Verilog -parseVerilogSrc = Verilog <$> many parseDescription +parseVerilogSrc = Verilog <$> many parseModDecl -- | Parse a 'String' containing verilog code. The parser currently only supports -- the subset of Verilog that is being generated randomly. |