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| author | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
| commit | cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (patch) | |
| tree | f00baaec9dcb747c27375af366ad9aec9d2dbe16 /src/VeriFuzz/Verilog/Preprocess.hs | |
| parent | 74a14ef30359e653259bf7139fe806548edefd14 (diff) | |
| download | verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.tar.gz verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.zip | |
Change name from VeriFuzz to VeriSmith
Diffstat (limited to 'src/VeriFuzz/Verilog/Preprocess.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Preprocess.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs index c783ac5..c30252b 100644 --- a/src/VeriFuzz/Verilog/Preprocess.hs +++ b/src/VeriFuzz/Verilog/Preprocess.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Preprocess +Module : VeriSmith.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog. Edits to the original code are warning fixes and formatting changes. -} -module VeriFuzz.Verilog.Preprocess +module VeriSmith.Verilog.Preprocess ( uncomment , preprocess ) |