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| author | Yann Herklotz <git@yannherklotz.com> | 2019-05-24 15:45:35 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-24 15:45:35 +0100 |
| commit | 14158fc4ef0809adbbf0b7fdd0c0d5e0fafc2435 (patch) | |
| tree | 9109005a77465d3d77d0d696107000bc39601066 /src/VeriFuzz/Verilog | |
| parent | 7e67a69693c4c0964f488d87dd94f64a2efe5409 (diff) | |
| download | verismith-14158fc4ef0809adbbf0b7fdd0c0d5e0fafc2435.tar.gz verismith-14158fc4ef0809adbbf0b7fdd0c0d5e0fafc2435.zip | |
Fix used wire check for clk
Diffstat (limited to 'src/VeriFuzz/Verilog')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 7a654fd..f201064 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -169,6 +169,9 @@ data Event = EId {-# UNPACK #-} !Identifier | EComb !Event !Event deriving (Eq, Show, Ord, Data) +instance Plated Event where + plate = uniplate + -- | Binary operators that are currently supported in the verilog generation. data BinaryOperator = BinPlus -- ^ @+@ | BinMinus -- ^ @-@ |