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| author | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:21 +0100 |
| commit | 19955b197a0a70d626c2e3c27dc91aabcb8b3e6a (patch) | |
| tree | effafe86068a7bf82c499945924e503d2130fd1d /src/VeriFuzz/Verilog | |
| parent | 66fc5b01be2011fa8f753231b1fc2243163c5bb8 (diff) | |
| download | verismith-19955b197a0a70d626c2e3c27dc91aabcb8b3e6a.tar.gz verismith-19955b197a0a70d626c2e3c27dc91aabcb8b3e6a.zip | |
Fix code generation for always blocks with or
Diffstat (limited to 'src/VeriFuzz/Verilog')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index e31866c..09d6d6f 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -146,7 +146,7 @@ expr (Str t ) = "\"" <> t <> "\"" showNum :: BitVec -> Text showNum (BitVec s n) = - minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") + "(" <> minus <> showT s <> "'h" <> T.pack (showHex (abs n) "") <> ")" where minus | signum n >= 0 = "" | otherwise = "-" @@ -214,8 +214,8 @@ eventRec (EExpr e) = expr e eventRec EAll = "*" eventRec (EPosEdge i) = "posedge " <> getIdentifier i eventRec (ENegEdge i) = "negedge " <> getIdentifier i -eventRec (EOr a b) = "(" <> eventRec a <> " or " <> eventRec b <> ")" -eventRec (EComb a b) = "(" <> eventRec a <> ", " <> eventRec b <> ")" +eventRec (EOr a b ) = eventRec a <> " or " <> eventRec b +eventRec (EComb a b ) = eventRec a <> ", " <> eventRec b -- | Generates verilog code for a 'Delay'. delay :: Delay -> Text |