Set column to 100

3 files changed, 23 insertions, 62 deletions

diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 338838f..34194a6 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -55,14 +55,7 @@ genDescription desc = genModuleDecl $ desc ^. getDescription
 -- | Generate the 'ModDecl' for a module and convert it to 'Text'.
 genModuleDecl :: ModDecl -> Text
 genModuleDecl m =
-  "module "
-    <> m
-    ^. moduleId
-    .  getIdentifier
-    <> ports
-    <> ";\n"
-    <> modI
-    <> "endmodule\n"
+  "module " <> m ^. moduleId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n"
  where
   ports | noIn && noOut = ""
         | otherwise     = "(" <> comma (genModPort <$> outIn) <> ")"
@@ -96,10 +89,9 @@ genModuleItem :: ModItem -> Text
 genModuleItem (ModCA ca) = genContAssign ca
 genModuleItem (ModInst (Identifier i) (Identifier name) conn) =
   i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n"
-genModuleItem (Initial stat) = "initial " <> genStmnt stat
-genModuleItem (Always  stat) = "always " <> genStmnt stat
-genModuleItem (Decl dir port) =
-  (maybe "" makePort dir) <> genPort port <> ";\n"
+genModuleItem (Initial stat ) = "initial " <> genStmnt stat
+genModuleItem (Always  stat ) = "always " <> genStmnt stat
+genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n"
   where makePort = (<> " ") . genPortDir
 
 -- | Generate continuous assignment
@@ -111,15 +103,13 @@ genContAssign (ContAssign val e) = "assign " <> name <> " = " <> expr <> ";\n"
 
 -- | Generate 'Expr' to 'Text'.
 genExpr :: Expr -> Text
-genExpr (BinOp eRhs bin eLhs) =
-  "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")"
-genExpr (Number s n) = showT s <> "'h" <> T.pack (showHex n "")
-genExpr (Id     i  ) = i ^. getIdentifier
-genExpr (Concat c  ) = "{" <> comma (genExpr <$> c) <> "}"
-genExpr (UnOp u e  ) = "(" <> genUnaryOperator u <> genExpr e <> ")"
-genExpr (Cond l t f) =
-  "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")"
-genExpr (Str t) = "\"" <> t <> "\""
+genExpr (BinOp eRhs bin eLhs) = "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")"
+genExpr (Number s n         ) = showT s <> "'h" <> T.pack (showHex n "")
+genExpr (Id     i           ) = i ^. getIdentifier
+genExpr (Concat c           ) = "{" <> comma (genExpr <$> c) <> "}"
+genExpr (UnOp u e           ) = "(" <> genUnaryOperator u <> genExpr e <> ")"
+genExpr (Cond l t f         ) = "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")"
+genExpr (Str t              ) = "\"" <> t <> "\""
 
 -- | Convert 'BinaryOperator' to 'Text'.
 genBinaryOperator :: BinaryOperator -> Text
@@ -177,13 +167,7 @@ genLVal :: LVal -> Text
 genLVal (RegId i       ) = i ^. getIdentifier
 genLVal (RegExpr i expr) = i ^. getIdentifier <> " [" <> genExpr expr <> "]"
 genLVal (RegSize i msb lsb) =
-  i
-    ^. getIdentifier
-    <> " ["
-    <> genConstExpr msb
-    <> ":"
-    <> genConstExpr lsb
-    <> "]"
+  i ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]"
 genLVal (RegConcat e) = "{" <> comma (genExpr <$> e) <> "}"
 
 genConstExpr :: ConstExpr -> Text
@@ -195,8 +179,7 @@ genPortType (Reg signed) | signed    = "reg signed"
                          | otherwise = "reg"
 
 genAssign :: Text -> Assign -> Text
-genAssign op (Assign r d e) =
-  genLVal r <> op <> maybe "" genDelay d <> genExpr e
+genAssign op (Assign r d e) = genLVal r <> op <> maybe "" genDelay d <> genExpr e
 
 genStmnt :: Stmnt -> Text
 genStmnt (TimeCtrl  d stat   ) = genDelay d <> " " <> defMap stat
@@ -209,9 +192,8 @@ genStmnt (TaskEnable     task) = genTask task <> ";\n"
 genStmnt (SysTaskEnable  task) = "$" <> genTask task <> ";\n"
 
 genTask :: Task -> Text
-genTask (Task name expr)
-  | null expr = i
-  | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")"
+genTask (Task name expr) | null expr = i
+                         | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")"
   where i = name ^. getIdentifier
 
 -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'.
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
index 53d219b..f910924 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -45,9 +45,7 @@ testBench = ModDecl
   [ regDecl "a"
   , regDecl "b"
   , wireDecl "c"
-  , ModInst "and"
-            "and_gate"
-            [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
+  , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
   , Initial $ SeqBlock
     [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
     , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index bca1c39..9f22faa 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -25,9 +25,7 @@ import           VeriFuzz.Verilog.CodeGen
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
 inPort i m = inInput
- where
-  inInput =
-    any (\a -> a ^. portName == i) $ m ^. modInPorts ++ m ^. modOutPorts
+  where inInput = any (\a -> a ^. portName == i) $ m ^. modInPorts ++ m ^. modOutPorts
 
 -- | Find the last assignment of a specific wire/reg to an expression, and
 -- returns that expression.
@@ -59,8 +57,7 @@ replace = (transformOf traverseExpr .) . idTrans
 nestId :: Identifier -> ModDecl -> ModDecl
 nestId i m
   | not $ inPort i m
-  = let expr = fromMaybe def . findAssign i $ m ^. modItems
-    in  m & get %~ replace i expr
+  = let expr = fromMaybe def . findAssign i $ m ^. modItems in m & get %~ replace i expr
   | otherwise
   = m
  where
@@ -73,13 +70,10 @@ nestSource i src = src & getVerilogSrc . traverse . getDescription %~ nestId i
 
 -- | Nest variables in the format @w[0-9]*@ up to a certain number.
 nestUpTo :: Int -> VerilogSrc -> VerilogSrc
-nestUpTo i src =
-  foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i]
+nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i]
 
 allVars :: ModDecl -> [Identifier]
-allVars m =
-  (m ^.. modOutPorts . traverse . portName)
-    ++ (m ^.. modInPorts . traverse . portName)
+allVars m = (m ^.. modOutPorts . traverse . portName) ++ (m ^.. modInPorts . traverse . portName)
 -- $setup
 -- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] [])
 -- >>> let main = (ModDecl "main" [] [] [])
@@ -100,16 +94,8 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
  where
   out   = Decl Nothing <$> m ^. modOutPorts
   regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg False)
-  inst  = ModInst (m ^. moduleId)
-                  (m ^. moduleId <> (Identifier . showT $ count + 1))
-                  conns
-  count =
-    length
-      .   filter (== m ^. moduleId)
-      $   main
-      ^.. modItems
-      .   traverse
-      .   modInstId
+  inst  = ModInst (m ^. moduleId) (m ^. moduleId <> (Identifier . showT $ count + 1)) conns
+  count = length . filter (== m ^. moduleId) $ main ^.. modItems . traverse . modInstId
   conns = ModConn . Id <$> allVars m
 
 -- | Instantiate without adding wire declarations. It also does not count the
@@ -151,9 +137,4 @@ makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt
  where
   ys    = Port Wire 90 . (flip makeIdFrom) "y" <$> [1 .. i]
   modIt = instantiateMod_ . modN <$> [1 .. i]
-  modN n =
-    m
-      &  moduleId
-      %~ makeIdFrom n
-      &  modOutPorts
-      .~ [Port Wire 90 (makeIdFrom n "y")]
+  modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]